Presentation
Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionWe propose hybrid GNN-based approaches towards highly accurate quality-of-result estimations with great generalization capability, specifically targeting logic synthesis optimization. The key idea is simultaneously leveraging spatio-temporal information from hardware designs and synthesis flows to forecast delay/area of various synthesis flows on different designs. The structural characteristics inside hardware designs are represented by GNNs; the temporal knowledge from synthesis flows can be imposed on hardware designs by combining a virtually added supernode or a sequence processing model with conventional GNN models. Evaluation shows the testing MAPE on designs seen and unseen during training are no more than 1.2% and 3.1%, respectively.