Close

Presentation

A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionHigh-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems, which require Power Controller Subsystems (PCS) to provide advanced multi-input, multi-output (MIMO) dynamic control of operating points and meet energy, power, and thermal constraints. In this paper, we propose ControlPULP, a PCS architecture that accelerates the Control Policy step exploiting parallel execution and achieving a speedup of 68\% (3.1x faster) against the base single-core configuration given a control interval of 500 $\mu$s and a nominal case of 72 controlled processors.