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PRIME: A PRocessing In Memory HardwareEmulation Framework
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionThis paper presentsPRIME, an extensible modeling, simulation, and emulation framework for on-chip Processing-In-Memory (PIM) design and assessment. Featuring a synthesizable RTL model, PRIME-based design encapsulates the fundamental in-/near-memory compute functionalities and can be mapped onto FPGA devices to ensure cycle-accurate and end-to-end correctness. A hybrid C/PIM assembly programming model isintroduced for the processor-PIM integrated system. We demonstrate an illustrative PIM system design on a Cyclone-IV FPGA and assess the performance and execution correctness of PIMlogic and macro instructions under both bit-parallel and bit-serial configurations, demonstrating the effectiveness of the proposed methodology.