Thermal and Signaling Considerations for 2.5D Integration of Arm-based 7nm High-Performance Systems
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
Description2.5D integration can be cost-effective to improve performance of computing systems but increasing package powers pose significant thermal challenges. We evaluate multiple design options for an Arm CPU-based 2.5D architecture focusing on thermals and die-to-die signaling at 7nm. We model an 80-core multi-die system using a thermal-signaling analysis methodology, and quantify trade-offs between die-to-die spacing, data-rate, and temperature. For an 8-die configuration, channel lengths of <1.5mm show a good balance: upto 37C lower temperature, while incurring a 65% lower data-rate versus 2D. Key insights are provided that can be useful for multi-die integration design, performance modeling, and thermal-aware task scheduling.