A Secure Design Methodology to Prevent Targeted Trojan Insertion During Fabrication
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionHardware Trojans are a threat when IC fabrication is outsourced to untrusted foundries. If the foundry can determine the correspondence between logical nodes of a design and the layout, they can use this knowledge to strategically choose target sites for Trojan insertion. In this work we propose a new synthesis approach to design programmable ASICs that is an improvement to existing state-of-the-art Trojan prevention approaches. We demonstrate our methodology on a number of benchmarks, validate the security of the designs produced and demonstrate area savings relative to embedded FPGA logic, which is otherwise required to secure monolithic ICs.