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Presentation

Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionThis paper presents a novel multi-phase clocking methodology targeting multi-threaded gate-level pipelined sequential circuits. Gate-level-pipelined circuits, such as present in superconductive digital electronics, require many path balancing registers to enable proper multi-threaded computation. The paper introduces a novel integer linear programming (ILP) algorithm to minimize the number of required registers given the number of available clock phases and a corresponding number of processing threads. We evaluated our approach using eight SFQ benchmark circuits through path balancing, clock tree synthesis (CTS), and place-and-route (PnR). Compared with fully-balanced approaches, which require a very large number of threads to achieve peak throughput, the proposed method reduces the number of path-balancing registers by 55.5% with two clock phases and up to 95.5% with ten clock phases. The CTS and PnR results show that the decrease in registers yields a decrease in total gate area by 40.6% and clock tree wire length by 54.9% with two clock phases, and by 69.6% and 69.8% with ten clock phases, respectively, despite the increase in the number of clock phases.

We compare our approach to the SOTA SFQ clocking solutions that rely on fully-path balanced circuits or dual slow/fast clocks. In addition to having lower overhead, a key benefit of the proposed approach is that it requires no fast clock. In particular, the clock frequency of the proposed multi-phased clocks is the same as the throughput of the circuit, avoiding the need to synthesize and route a high-speed clock.