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Presentation

SoC Platform for Heterogeneous Multiple IP Core Evaluation
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionDeveloping own IP and ASIC with dedicated software is one of the ways to create proper application specific AI solution. Proposed IP evaluation platform supports IP integration to SoC with NOC, chip level verification, IP integrated SoC implementation, SoC test production, SoC evaluation board development, and SoC evaluation software development. The platform can integrate multiple IP to single SoC and evaluate each IP individually. Evaluation platform and developing methodology reduces development cost significantly. Six heterogeneous IP integrated SoC was designed and under test chip evaluation. We have achieved 73% reduction of total chip area, development efforts, compared to individual chip developments.