Leveraging Layout-based Effects for Locking Analog ICs
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionWhile various obfuscation methods exist in the digital domain, techniques for protecting intellectual property (IP) in the analog domain are mostly overlooked. This paper is the first to show a method to secure analog IP by exploiting layout-based effects that are seen as undesirable detractors in IC design. The proposed technique is applied for locking an Operational Transconductance Amplifier. The results show up to 130dB degradation in open-loop gain. We justify the non-effectiveness of reverse-engineering efforts for at-
tacking our approach. Our technique employs regular MOSFETs and requires neither changes to the IC fabrication process nor any coordination with untrusted foundries.