An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionThis paper shows a ReRAM accelerator for neural architecture search (NAS) optimized multi-bitwidth neural networks. An energyefficient yet bitwidth-scalable configuration is developed for each ReRAM-based MAC. Moreover, space-time multiplexed ADCs are utilized to minimize signal conversion related overhead in each ReRAM-based PE without accuracy loss. Additionally, a systolic data reuse is deployed in ReRAM-based PE array with further performance improvement. Experiments based on NAS optimized neural networks show that the proposed multi-bitwidth ReRAM accelerator can achieve TOP energy efficiency of 17.22TOPS/W, which has 3.5× and 1.44× improvement when compared with existing