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Presentation

CAD for Hardware Security Workshop (CAD4Sec)
TimeSunday, July 10th8am - 5pm PDT
Location3006, Level 3
Event Type
Workshop
Topics
Security
DescriptionSecurity vulnerabilities in hardware designs are catastrophic since it is almost impossible to patch them once they are fabricated. Recent studies have shown many vulnerabilities in SoC hardware implementations, including side-channel leakage, information leakage, access control violations, malicious functionality, etc. These attacks can effectively bypass the built-in security mechanisms and put chips or systems at risk. Ensuring the security of hardware designs is challenging due to their huge complexity, aggressive time to markets, and the variety of attacks. Since designers may not have sufficient knowledge about the security requirements due to the huge complexity of SoC designs and their attack surfaces, it is difficult to manually analyze the design implementation in different levels of abstractions. Therefore, the semiconductor industry and system integrators are looking for a set of metrics, reusable security solutions, and automatic computer-aided design (CAD) tools to aid analysis, identifying, root-causing, and mitigating SoC security problems.
Vulnerabilities in SoCs are due to design mistakes, lack of security understandings, design transformations, various attack surfaces, and malicious intents. Further, exiting CAD tools are used in SoC design flow can introduce additional vulnerabilities in the SoCs unintentionally. For example, some design practices/choices may make the design vulnerable to timing and power side-channel leakage. Not only will these vulnerabilities move from one level of abstraction to another, but unique vulnerabilities can also be introduced during design transformations. For example, an RTL design with power side-channel issues can suffer from access control issues when it is synthesized to gate-level, and design-for-debug infrastructure will be inserted. Therefore, it is essential to have automatic CAD solutions to be able to analyze the security of SoCs in a comprehensive manner, in all levels of abstractions, and against all existing threats (e.g., fault-injection, side-channel, and hardware Trojan attacks). CAD tools should be able to access the security of the design in the pre-silicon stage and suggest possible countermeasures while still, it is possible to modify the design and address the potential vulnerabilities.
CAD4Sec will invite experts from industry (like Synopsys, Cadence, Google, Analog Devices, Mentor Graphics), academia, and government (like DARPA, NAVY, AFRL) to shed light on the need for and the recent progress on the development of automatic security CAD solutions in all levels of abstractions (i.e., C/C++, RTL, gate-level, and layout). The workshop will include demos on the recent CAD for security tools to detect various vulnerabilities. There will be technical talks and a panel consisting of experts in the field to talk about the road map for CAD for security development. The CAD4Sec workshop will cover the following:
• CAD for power/timing side-channel vulnerability assessment
• CAD for electromagnetic radiation vulnerability assessment
• CAD for fault-injection vulnerability evaluation
• CAD for automatic security property generation
• CAD for security equivalence checking between different design abstractions
• CAD for security equivalence checking between different SoCs
• CAD for Optical/microprobing/nanoprobing probing for assurance
• CAD for (Anti-)Reverse engineering and physical attacks
• CAD for FPGA Bitstream protection and vulnerabilities
• CAD for Trojans detection and prevention