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Presenter

Yibo Lin
Peking University
Presentations
Research Manuscript
A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
EDA
Timing and Low Power Design
Research Manuscript
Differentiable Timing Driven Global Placement
EDA
Physical Design and Verification, Lithography and DFM
Research Manuscript
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity and Clock Feasibility
Design
Physical Design and Verification, Lithography and DFM
Research Manuscript
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
EDA
Manufacturing Test and Reliability
Research Manuscript
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
EDA
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM