Session
Hardware security potpourri: logic locking, hardware Trojans, and memory attacks
Session Chair
Event TypeResearch Manuscript
Hardware Security: Attack and Defense
Hardware Security: Primitives, Architecture, Design & Test
AI
Security
TimeWednesday, July 13th3:30pm - 5:30pm PDT
Location3006, Level 3
DescriptionThis session includes presentations from leading-edge research on logic locking techniques, hardware Trojans and memory attacks. Two logic locking papers investigate locking mechanisms at the register transfer level (RTL) and via clock gating. In the third presentation, RTL modules are used among multiple reconfigurable fabrics to protect intellectual property. Trojan detection techniques for stealthy Trojans are presented in the fourth paper. The fifth presentation shows a machine learning based PCB assurance technique. The session ends with the presentation of a novel countermeasure to protect memory against inconsistent write attacks.
Presentations
| 3:30pm - 3:50pm PDT | Designing ML-Resilient Locking at Register-Transfer Level | |
| 3:50pm - 4:10pm PDT | O'Clock: Lock the Clock via Clock-gating for SoC IP Protection | |
| 4:10pm - 4:30pm PDT | ALICE: An Automatic Design Flow for eFPGA Redaction | |
| 4:30pm - 4:50pm PDT | DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis | |
| 4:50pm - 5:10pm PDT | VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework | |
| 5:10pm - 5:30pm PDT | CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks |