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Session

Research Manuscript: Iterate and Scale: Designing Stronger and Safer Embedded Systems
Event TypeResearch Manuscript
Keywords
Embedded System Design Methodologies
Time-Critical System Design
Topics
Embedded Systems
RISC-V
TimeTuesday, July 12th1:30pm - 3:00pm PDT
Location3004, Level 3
DescriptionThis session focuses on exciting new ways to effectively analyze and design high-performance and low-power embedded systems. The first paper proposes a highly portable and feature-rich ISA Extensions interface that supports custom control flow, decoupled execution, multi-cycle instructions, and memory transactions in RISC-V processors. The second paper proposes a methodology that enables automated safety analysis in the design of safety-critical systems. The third paper proposes a custom symbolic simulator to enable hardware-software co-analysis and the development of hardware and software optimizations for low-power embedded systems.