Research Manuscript: Keep moving up and looking sideways with verification boosters!
Event TypeResearch Manuscript
Design Verification and Validation
TimeThursday, July 14th3:30pm - 5:30pm PDT
Location3000, Level 3
DescriptionThis section reflects the latest trends in verification and validation. It introduces state-of-the-art software-level verification methodologies and symbolic execution tools to accelerate bug hunting in high-level hardware generators and transaction-level peripherals. It presents the first formal verification method for modular multipliers. It further illustrates advanced learning-based techniques that extend the envelope of verification and validation in practical applications, including security validation of logic-locked hardware IPs and active learning to accelerate IC yield analysis and optimization. The session finale goes beyond EDA with the introduction of a boosted, neural network-based barrier certificate synthesis method using collaborative learning for cyber-physical system verification.