Session
Novel approaches for scaling routing and DFM challenges
Session Chairs
Event TypeResearch Manuscript
Physical Design and Verification, Lithography and DFM
EDA
TimeThursday, July 14th10:30am - 12:00pm PDT
Location3007, Level 3
DescriptionThis session focuses on novel approaches for routing and lithography modeling. The first paper presents a new flip-chip router based on Y-architecture. The second paper introduces a federated learning based method for routability estimation. The third paper presents a GPU-accelerated framework equipped with spatial attention for inverse lithography technology, while the last paper introduces a fast neural network based method for lithography simulation.
Presentations
10:30am - 10:52am PDT | Y-architecture-based Flip-Chip Routing with Dynamic Programming-based Bend Minimization | |
10:52am - 11:15am PDT | Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data | |
11:15am - 11:37am PDT | A2-ILT: GPU Accelerated ILT with Spatial Attention Mechanism | |
11:37am - 12:00pm PDT | Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks |