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Research Manuscript: Learn about advanced placement algorithms for hyperscaler chips!
Session Chair
Event TypeResearch Manuscript
Keywords
Physical Design and Verification, Lithography and DFM
Topics
Design
TimeWednesday, July 13th1:30pm - 3:00pm PDT
Location3007, Level 3
DescriptionThis session introduces new placement algorithms for wafer scale engines and FPGAs. It starts with the paper that presents a partitioning and placement framework for finite element model on wafer-scale engines. The next three papers consider large-scale heterogeneous FPGAs and present various and advanced placements methods.