Session

DescriptionLogic synthesis is one of the most important steps in chip design: yet too complex and expensive. This session provides new solutions to such old challenges. The first proposes an iterative flow for logic synthesis, while the second aims at using LUT-based optimization for ASIC synthesis. The third paper shifts the focus on the long runtimes, proposing to accelerate logic rewriting with GPUs. The next two papers provide techniques to optimize approximate logic synthesis. The sixth paper provides a solution to insert buffer and slitter cells for the new adiabatic quantum-flux parametron (AQFP) technology.