Session
Machine Learning for Synthesis and Synthesis for Machine Learning
Event TypeResearch Manuscript
RTL/Logic Level and High-level Synthesis
AI
EDA
TimeTuesday, July 12th10:30am - 12:00pm PDT
Location3004, Level 3
DescriptionThis session shows that logic synthesis and high-level synthesis (on one side) and machine learning (on the other side) are now deeply intertwined: one cannot live without the other.
In the first two papers, graph neural networks support the designers in the optimization process of accelerators, enabling better predictions. The third paper applies graph neural networks to gate-level netlist representation extraction. The last paper shows, instead, how high-level synthesis can help design better accelerators for machine learning.
In the first two papers, graph neural networks support the designers in the optimization process of accelerators, enabling better predictions. The third paper applies graph neural networks to gate-level netlist representation extraction. The last paper shows, instead, how high-level synthesis can help design better accelerators for machine learning.
Presentations
| 10:30am - 10:53am PDT | High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing | |
| 10:53am - 11:15am PDT | Automated Accelerator Optimization Aided by Graph Neural Networks | |
| 11:15am - 11:37am PDT | Functionality Matters in Netlist Representation Learning | |
| 11:37am - 12:00pm PDT | EMS: Efficient Memory Subsystem Synthesis for Spatial Accelerators |