Session

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Research Manuscript: So You Want a Better Design? Go with Faster Timing and Lower Power Please!

Session Chairs

Karthi Duraisamy

Synopsys

Cong (Callie) Hao

Georgia Institute of Technology

Event TypeResearch Manuscript

Keywords

Topics

TimeThursday, July 14th3:30pm - 5:30pm PDT

Location3007, Level 3

DescriptionThis session focuses on how to derive a better design in terms of timing performance and power efficiency. AI/ML methods are continuously being used in the EDA industry and so is the case in this session. Six papers are presented in this session, with half focusing on timing and half focusing on power. The first three papers develop innovative AI/ML methods to improve the timing performance and the last three papers develop AI/ML methods to improve power efficiency.

Presentations

3:30pm - 3:50pm PDT	A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction Authors Zizheng Guo Mingjie Liu Jiaqi Gu Shuhan Zhang David Z. Pan Yibo Lin
3:50pm - 4:10pm PDT	Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network Authors He Xu Zhiyong Fu Yao Wang Chang Liu Yang Guo
4:10pm - 4:30pm PDT	Timing Macro Modeling with Graph Neural Networks Authors Kevin Kai-Chun Chang Chun-Yao Chiang Pei-Yu Lee Iris Hui-Ru Jiang
4:30pm - 4:50pm PDT	Worst-Case Dynamic Power Distribution Network Noise Prediction Using Convolutional Neural Network Authors Xiao Dong Yufei Chen Xunzhao Yin Cheng Zhuo
4:50pm - 5:10pm PDT	GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement Authors Yanqing Zhang Haoxing Ren Akshay Sridharan Brucek Khailany
5:10pm - 5:30pm PDT	PPATuner: Pareto-driven Tool Parameter Auto-tuning in Physical Design via Gaussian Process Transfer Learning Authors Hao Geng Qi Xu Tsung-Yi Ho Bei Yu