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Research Manuscript: Cool Interconnects for Cool Accelerators on Top of Congestion Free Place & Route
Event TypeResearch Manuscript
Keywords
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM
Topics
EDA
TimeTuesday, July 12th10:30am - 12:00pm PDT
Location3007, Level 3
DescriptionData transport in advanced system-on-chip architectures significantly contributes to the power consumption and thermal footprint of the overall integrated system. Furthermore, today’s VLSI solutions are severely challenged by provisioning congestion free routing and placement. This session will introduce you to latest results on thermal-aware optical-electrical routing codesign flows that minimize power dissipation and nanophotonic technologies for optical neural networks (ONN), as well as software configurable NoCs for wearable AI accelerators and hypergraph neural network models for routability-driven placement. Common denominators are the applicability of electro-optical technologies and machine learning approaches for low power on-chip signal communication as well as intra accelerator interconnects.