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Session

Research Manuscript: Fantastic SoCs and What to Learn!
Event TypeResearch Manuscript
Keywords
System-on-Chip Design Methodology
Topics
EDA
TimeTuesday, July 12th1:30pm - 3:00pm PDT
Location3007, Level 3
DescriptionThis session presents four papers on the state-of-the-art for system-on-chip (SoC) design, modeling, mapping, and optimization. The first paper develops a novel cost model to explore emerging multi-chiplet systems, followed by the second paper that proposes a scalable compiler-based approach for mapping complex loop kernels on CGRAs. The third paper develops a fast parameter tuning framework to quickly find the optimal configurations in a system with massive design space, followed by the fourth paper that develops a methodology for effectively mapping DSL applications to hardware accelerators.