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Session

Research Manuscript: Optimizing Neural Network Hardware: Sparsity, Reuse and System
Event TypeResearch Manuscript
Keywords
AI/ML Design: Circuits and Architecture
Topics
Design
TimeTuesday, July 12th1:30pm - 3:00pm PDT
Location3002, Level 3
DescriptionThe performance of AI accelerators is determined by many factors, ranging from algorithm to architecture to system. This section focus on efficient techniques to optimize the performance of deep neural network hardware, from the perspective of sparsity, data reuse and system integration.