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Session

Research Manuscript: Orders of Magnitude Acceleration
Event TypeResearch Manuscript
Keywords
SoC, Heterogeneous, and Reconfigurable Architectures
Topics
Design
TimeTuesday, July 12th3:30pm - 5:30pm PDT
Location3005, Level 3
DescriptionThe session starts with a near-storage accelerator for mass spectrum clustering. It continues with a high-throughput and scalable data compression architecture targeted for FPGA-enabled data centers. The third presentation accelerates transformers by using an evolutionary algorithm and exploiting sparsity. Afterwards, a fast and energy-efficient EMVS accelerator is introduced that realizes the most critical and time-consuming stages on an FPGA. The final two presentations target CGRAs with an ML-based method to accelerate the mapping of loops onto CGRAs by an order of magnitude without compromising the mapping quality, and an execution model and co-designed CGRA design that supports fine-/coarse-grained parallelism for operators/tasks, respectively.