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Session

Research Manuscript: From Cores to Memory and Back
Event TypeResearch Manuscript
Keywords
SoC, Heterogeneous, and Reconfigurable Architectures
Topics
Design
TimeThursday, July 14th1:30pm - 3:00pm PDT
Location3005, Level 3
DescriptionThis session presents four innovative contributions related to cores and memories for SoC systems. The first paper analyzes data-prefetching techniques for commercial in-order cores followed by a paper on improving the performance of Propane NVM systems using DDR5 memory. The third contribution describes a framework for the processing of graphs using hybrid memory cubes. The fourth contribution AxoNN introduces techniques for energy-aware execution of neural network inference on multi-accelerator SoCs.