Engineering Tracks, Front-End Design: Taming the Validation Dragon with Formal and Static Verification
Event TypeEngineering Tracks, Front-End Design
Front-End Design
TimeMonday, July 11th10:30am - 12:00pm PDT
Location2010, Level 2
DescriptionWith validation's seemingly infinite appetite to consume engineering resources, formal and static methods have become a crucial tool to enable closure of complex designs. This session covers the still-growing role of formal and static methods in various areas of front-end design: microarchitecture and functional correctness; clocks, resets, and metastability; and analog/mixed-signal verification.