Close
 

Session

Back-End Design, Engineering Tracks: Power Play Musings
Session Chair
Badhri Uppiliappan
Analog Devices
Event TypeBack-End Design, Engineering Tracks
Topics
Back-End Design
TimeTuesday, July 12th10:30am - 12:00pm PDT
Location2008, Level 2
Presentations
10:30am - 10:45am PDTPrototyping and verification of Power Delivery network for a Foveros 3DIC design.
Presenters
Amartya Mazumdar
Vineet Sreekumar
Basavaraj Kanthi
Chandrahas Alla
Manish Kumar
Alina Sebastian
Tapan Ganpule
10:45am - 11:00am PDTExperimental Validation of a Novel Methodology for Electromigration Assessment in On-chip Power Grids
Presenter
Valeriy Sukharev
11:00am - 11:15am PDTVFopt: ML-Based Optimization Voltage/Frequency Exploration System
Presenters
Jaemin Seo
Yun Heo
Kunyuk Kang
Varun Gunnala
Donghyun Lee
11:15am - 11:30am PDTOn-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis using STA native timing engine
Presenter
Dongchul Kim
11:30am - 11:45am PDTIR drop fixing using Timing ECO integrated solution with IR Signoff tool
Presenters
sahil sukheja
Amruthavalli Sreekantapuram
Mathew Kaipanatu
11:45am - 12:00pm PDTSigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Presenters
Anusha Vemuri
Emmanuel Chao
Santosh Santosh
Piyush Jain
Yatender Mishra