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Session

Engineering Tracks, IP: When RTL doesn't cut it: topics in analog, mixed signal and custom IP design
Event TypeEngineering Tracks, IP
Topics
AI
IP
TimeMonday, July 11th3:30pm - 5:00pm PDT
Location2012, Level 2
DescriptionTransistor level design is more important than ever with the complex physics of advanced nodes and market demand for differentiation driving designers to use the full capability of a process. This session showcases novel developments in the areas of analog, mixed signal and custom IP design. It covers a variety of topics such as high sigma Monte Carlo simulations, symbolic verification techniques, DFM, PLL architectures, using machine learning for mixed signal modeling, and verification of analog ML IP.