Engineering Tracks, IP: The interdependence between ML/AI and chip design automation
Event TypeEngineering Tracks, IP
TimeTuesday, July 12th1:30pm - 3:00pm PDT
Location2012, Level 2
DescriptionThe ever-increasing popularity and practical applications of Machine Learning and AI seen within the past decade was unlocked through unprecedented computational capabilities of modern GPUs. Now, AI and ML are increasingly being tapped into for handling some of the most complex steps in designing state-of-the-art chips to improve performance, quality, and time to market, as evident from the keynote presentations in DAC58.
This session includes presentations focusing on addressing the requirements of memory-intensive use cases (multimedia, graphics, AI training and inference) through maximizing the NOC utilization, as well as in-memory-computation hardware. The session also includes presentations using AI/ML to enhance layout and design verification quality and turn-around time. Finally, this session includes submissions aiming to reduce design complexity and turnaround time by generalizing and automating ISO compliance verification IP and module interface design.