Session

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Engineering Track Poster, Engineering Tracks: Engineering Track Poster Reception - Monday

Event TypeEngineering Track Poster, Engineering Tracks

Topics

TimeMonday, July 11th5:00pm - 6:00pm PDT

LocationLevel 2 Exhibit Hall

Presentations

4G/5G Encoder-Decoder IP Use Cases and Performance Validation in Emulation and Post Silicon using Portable Stimulus Standard’s HSI Presenters Suresh Vasu Vinit Shenoy Nithin Venkatesh Suhas Reddy Luis Campos Joydeep Maitra
Automated Timing-aware Dynamic Voltage Drop ECO Presenters Seonghun Jeong Dongyoun Yi Byunghyun Lee Sun ik Heo Len Hsu KH Kim Anusha Gummana Sankar Ramachandran
Back End of Line Process-aware Static Timing Analysis Presenter Mijeong Lim
Billion Instance Timing Sign-off Presenters Tim Helvey David Lawson
CDC Signoff Flow with DFT Logic Presenters Herbert Blesse Vardan Vardanyan
Cell EM aware Design Optimization Presenters Minseok Kang Kwangseok Choi Jinmo Jung Vivek Panure
Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction Presenters Ingeol Lee Jaehoon Kim Jun Seomun Sangyun Kim
Clustering Characterization Condition for Multi-bit Cell Presenters Woojin Jung Mintae Lee Soyeong Lee Jaieun Baek Wook Kim Keunho Lee Inhwan Song Yeon-Ho Im
Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design Presenters Madan Lal Sanjana Kale Shubham Lunawat Hemant Jain NIjesh C
DVD Diagnostics - Debugging Dynamic IR problems using Advanced Analytics Presenters Ilhan Hatirnaz Manmeet Singh
A Dynamic approach towards NOC Performance Verification in Pre-Silicon and Overcome the traditional Overheads Presenters Suresh Vasu Zafar Mohammad Thirumala Chakravarthy
Enabling a 20B-transistor Chip with Unit Level Timing Abstraction Presenters Adil Bhanji Chaitanya Peddawad Jack DiLullo Jason Morsey Michael Wood Ravichander Ledalla
Efficient Custom Logic P&R Flow using Virtual Hierarchy Presenters Doh-young Kim Youngjai Ryu Dongmin Lee Hun Lim Youngjin Cho Keunbong Lee Jungmin Choi
Formal Verification of Deep Neural Networks in Hardware Presenters Shreyansh Agrawal Surinder Sood Kenneth Roe
Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification Presenters Amit Goldie Ankush Bagotra Himanshu Kathuria Sampath Amarasinghe
Learnings from RDC Sign-Off on Low Power SoC Presenters Jieun Ahn Seongdeuk Jo Woohyun Son Kiseok Bae Mijung Noh Hyobeen Park Vikas Sachdeva
Library Analytics and Library Partitioning [LALP] for PPA Efficiency Presenters Sourav Saha Rushabh Shah Raghunandana R Shrikrishna Gawade Divya M Praveen Ghagare
Logfile Error Analysis: How to make sense of millions of lines of logfiles using CHEW_LOGS (Check Errors and Warning in Logfiles) Presenter Thomas Arneberg
Machine Learning Techniques for PDK Development Efficiency Presenters Nolan Pavek Romain Feuillette Vivienne Miller
New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design Presenters SeaEun Park SeongWook Lee Jungyun Choi
On-Chip PDN-Aware Simulation Methodology with RC Network Reduction Presenters Juho Jeon Seunghyeok Kwon Donghyun Kang Seonghyeon Park Mingu Kang Hwapyong Kim Haeun Jeon Youngho Seo Yujin Lee Seungjae Lee Soeun Sin Sojin Kim Botak Lim Daehee Lee Kwangok Jeong Hyuckjoon Kwon Jungyun Choi
Overcoming IR Challenges for reticle sized ASIC in new architecture and advanced node Presenters Swati Jindal Anand Iyer Pranav Ranganathan
Power solution to maximize performance-per-watt for GPGPU Presenters Shixuan Que Ling Sun Lili Dai Yuanyuan Ling Zhenbang Wang Sushil Mittal
Power-Thermal Co-simulation for More Accurately DC IRDrop and temperature distribution of GPGPU’s PCB and Package Presenters Shuyuan Guan zhenghao chu Calvin Chow
Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors Presenters Nagu Dhanwada Karthik Swaminathan Kartik Acharya Khajista Fattu Ramon Bertran Anurag Umbarkar
Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios Presenters Abhinav Parashar Harish Maruthiyodan Gaurav Kumar Varshney
ROHD: The Rapid Open Hardware Development Framework Presenter Max Korbel
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage Presenter Ashutosh Mishra
Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC Presenters Amanjit Panda Nanda Pallari Varun Sharma
Static Timing and Power Analysis with Process Space Exploration Presenters Changho Han Chul Rim Mijeong Lim Sun Ik Heo Asheesh Baghel Ruijing Shen Mayur Bubna Li Ding
SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION Presenters Bhushan Parikh Shaman Narayana
Time Interleaving of Analog to Digital Converters Calibration Techniques Presenter Adeel Adhm
Using Formal Verification Signoff for Digital IP Presenter David Vincenzoni
Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology Presenters Harsh Sharma Narava Kumar Sagar Jogur Kavya S Avinash Chaudhary Sooraj Sekhar Einar Ellingsen Ruchi Shankar Stefan Dannenberger Mikael Kromer Harish Maruthiyodan Anand G Lakshmanan Balasubramanian