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Session

Engineering Track Poster, Engineering Tracks: Engineering Track Poster Reception - Monday
Event TypeEngineering Track Poster, Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
TimeMonday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Presentations
4G/5G Encoder-Decoder IP Use Cases and Performance Validation in Emulation and Post Silicon using Portable Stimulus Standard’s HSI
Automated Timing-aware Dynamic Voltage Drop ECO
Back End of Line Process-aware Static Timing Analysis
Presenter
Billion Instance Timing Sign-off
CDC Signoff Flow with DFT Logic
Cell EM aware Design Optimization
Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Clustering Characterization Condition for Multi-bit Cell
Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
DVD Diagnostics - Debugging Dynamic IR problems using Advanced Analytics
A Dynamic approach towards NOC Performance Verification in Pre-Silicon and Overcome the traditional Overheads
Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Efficient Custom Logic P&R Flow using Virtual Hierarchy
Formal Verification of Deep Neural Networks in Hardware
Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Learnings from RDC Sign-Off on Low Power SoC
Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Logfile Error Analysis: How to make sense of millions of lines of logfiles using CHEW_LOGS (Check Errors and Warning in Logfiles)
Machine Learning Techniques for PDK Development Efficiency
New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Overcoming IR Challenges for reticle sized ASIC in new architecture and advanced node
Power solution to maximize performance-per-watt for GPGPU
Power-Thermal Co-simulation for More Accurately DC IRDrop and temperature distribution of GPGPU’s PCB and Package
Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors
Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
ROHD: The Rapid Open Hardware Development Framework
Presenter
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage
Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC
Static Timing and Power Analysis with Process Space Exploration
SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
Time Interleaving of Analog to Digital Converters Calibration Techniques
Presenter
Using Formal Verification Signoff for Digital IP
Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology