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Session

Engineering Track Poster, Engineering Tracks: Engineering Track Poster Reception - Tuesday
Event TypeEngineering Track Poster, Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
TimeTuesday, July 12th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Presentations
Automated DCAP and filler cell insertion with embedded Design for Inspection (DFI) Sensors
Building a Robust Power Grid for Multi Million SoC using RedHawk-SC Early PG Grid Analysis
Challenges of Integrating and Testing a Design with Multiple IP Vendors
A Comprehensive Electromagnetic Analysis for Transmission Line in High-Speed AMS Design
COMPUTE-IN-MEMORY SRAM ARRAY WITH NEW ENERGY EFFICIENT RECONFIGURABLE DATA SENSING TECHNIQUE FOR HARDWARE ACCELERATORS
Concurrent Package + Interposer + Die IR Analysis using Ansys’ RedHawk-SC Electrothermal
Dealing with Silicon Aging in Digital Implementation using Library Metrics
Design Timing Effects of Layer-to-Layer Interconnect Skew
Dynamic CDC Verification with Enhanced Jitter Modeling in Synchronizers
Efficient read/write turn-around policy of LPDDR5 memory controller
Efficient Low Power Isolation Handling for Pre-Silicon Emulation
Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model
Fast Design Space Exploration using RTL Architect for DRAM Designs
Generation And Selection Of Universally Routable Via Mesh Specifications
A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
In-design IR drop convergence with Ansys RHSC and SNPS fusion compiler
Integrating Liberty model validation, analysis, and visualization as part of library design and characterization
Left Shift of Multi-Cycle Paths and False Paths Signoff By Formal and Dynamic Simulation Methodologies with significant ROI
Low Power Verification Challenges of Hierarchical UPF in Discrete Graphics SoC Design
Minimum repeater addition ECOs for power efficient designs
PostMask functional ECO Implementation flow using Programmable cells
ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
SDR (Simulation-Driven Routing): A Solution to Get Electromigration Compliant Routing
Shift Left DFT Sign-off Methodology for Edge AI Processor
Solving Antenna Errors for Hierarchical Designs
TCP/IP Hardware Stack Design and Verification Challenges
Thermal Aware Memory Controller Design with Chip Package System Simulation
Towards an Automated Workflow for Link-level Exploration and Optimization in the Domain of All-to-All Optical Networks
A unified IP QA methodology to improve validation coverage and throughput
Workflow Automation for SoC Performance Verification
XMAS: An Efficient Customizable Flow for Crossbarred-Memristor Architecture Search