Session

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Engineering Track Poster, Engineering Tracks: Engineering Track Poster Reception - Wednesday

Event TypeEngineering Track Poster, Engineering Tracks

Topics

TimeWednesday, July 13th5:00pm - 6:00pm PDT

LocationLevel 2 Exhibit Hall

Presentations

AI assisted smart analysis (AISA) for system level issue localization in post silicon validation Presenters Amaresh Chellapilla Nagi Reddy Emani Pandithurai Sangaiyah
AI-based Neural network approach for performance estimation of complex System-on-Chip Presenters Manoj Munigala surinder sood Madhusudhan N
Automated Timing Degradation Recovery in Incremental Tape-Out of High-Speed CPU Design Presenters Gopalakrishnan Sadagopan Senthil Ravi
Chatbot as a Virtual Assistant to Retrieve Information from Datasheets Presenters khaled Salah Esraa Mohsen Anss Khaled Abdelrhman Tarek Menna Hussien Mona Mahmoud Haidy Samir
Clock Scripting for Reliable Design Flow Presenter Gary Ellis
Converging the “World’s Densest” PNR design on TSMC N5P - Beating Custom SRAM transistor densities in synthesized Place & Routed Design Presenters Bhuoender Kumar Guneet Singh Raghav Gupta Goutami Aenuganti
Design Intent Driven Analog Routing Methodology Presenters Rajeev Singh Devendra Gupta Atul Bhargava Gautam Kumar Alexandre Soyer Vishesh Kumar
Diagnosis of Faults by Fault Simulation on PCIe Presenters Priyanka Gharat Shikhadevi Katharia Sushant Gawade
Efficient stimulus generation techniques for a UVM TB Presenter Pavan Yeluri
Formal based Automation Framework to Verify Coherent Connectivity of Multi-instance IPs Presenters Somesh Gode Malav Shrikant Shah Vinod Paparaju Abhinandan Sharma
FPopt: ML-Based Chip Floorplan Optimization Presenters Jaemin Seo Yun Heo Kunhyuk Kang Seonil Brian Choi Joe R Walston Varun Gunnala Donghyun Lee
History based Physical Synthesis Presenters Lakshmi Reddy Cindy Washburn nancy Zhou Alex Suess Ben Trombley Dan Lewis Josiah Hamilton
FSDB based Self-Gating technique for Power saving and FEV Verification approaches Presenters Aman Jain Sidarth Panda
High speed, low power hybrid ADC for direct to RF sampling applications Presenter Ken Potts
Improving Power Grid IR drop with an automated layout enhancement flow Presenters Sumit Jha Greg Davis Fady Fouad Gurpreet Lamba Smitha Kamathi jeffery Wilson
The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud Presenters Taeil Kim Naya Ha Jongho Kim Kyungtae Do Sangyun Kim
Merging Formal and Simulation Verification Metrics for Coverage Closure Presenter Pradeep Valipe
Minimize Power Consumption with A Novel Power ECO Flow Presenters Jianfeng Liu Eunju Hwang YeongYeong Shin Seokhoon Kim Jun Seomun Sangyun Kim
Mitigation of Soft-Errors in Storage Elements through Layout and Circuit Design Techniques Presenters Sumit Wadkar Shrisagar Dwivedi Parag Upadhyay
A Novel Duty-Cycle Adjuster Circuit , To Be Used As Part Of Automatic Clock Duty-Cycle Corrector Circuit Presenter Ayan Dutta
On-Chip embedded sensor in 18nm technology to monitor the effects of process variations on standard cells logic and interconnect delays Presenter Rohit Goel
Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC Presenters Sooraj Sekhar Harsh Sharma Akshay Revankar Siddharth Sarin Pavan Kumar Kulkarni Ruchi Shankar Harish Maruthiyodan Shalini Eswaran Gaurav Varshney Lakshmanan Balasubramanian
Path-Finding Through Variability-Aware DTCO-Flow Presenters Markus Karner Gerhard Rzepa Oskar Baumgartner Zlatan Stanojevic
Performance Optimization of Embedded FPGA Presenter Michael Ji
Porting software to hardware using XLS/DSLX Presenter Johan Euphrosine
Process Monitoring Blocks - for Monitoring Analog Performance Presenters Priya Talwar Anand Mishra
Science Without Boundaries: A Proven Method To Achieve Seamless Design Collaboration between Cross-Institutional Project Teams Presenters Carl Grace Simon Rance
Shift Left Performance Verification using Formal Methods for ML ASICs Presenter Puneet Anand
Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement Presenters Lippika Parwani Bhupendra Singh Gaurav Goel Frederic Esteban
Technology co-optimization to mitigate the technology impact of context-based timing in standard Cell library Presenters VENY MAHAJAN ANAND MISHRA
Physically Unclonable Function Compliant with ISO/IEC 20897-1:2020 Presenters Sylvain Guilley Guillaume Patrigeon
Is Front-End Analog Design Automation an NP-type or simply a P-type problem ? Presenter Ramy ISKANDER