Engineering Track Poster, Engineering Tracks: Engineering Track Poster Reception - Wednesday
Event TypeEngineering Track Poster, Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
TimeWednesday, July 13th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
AI-based Neural network approach for performance estimation of complex System-on-Chip
Automated Timing Degradation Recovery in Incremental Tape-Out of High-Speed CPU Design
Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
Clock Scripting for Reliable Design Flow
Converging the “World’s Densest” PNR design on TSMC N5P - Beating Custom SRAM transistor densities in synthesized Place & Routed Design
Design Intent Driven Analog Routing Methodology
Diagnosis of Faults by Fault Simulation on PCIe
Efficient stimulus generation techniques for a UVM TB
Formal based Automation Framework to Verify Coherent Connectivity of Multi-instance IPs
FPopt: ML-Based Chip Floorplan Optimization
History based Physical Synthesis
FSDB based Self-Gating technique for Power saving and FEV Verification approaches
High speed, low power hybrid ADC for direct to RF sampling applications
Improving Power Grid IR drop with an automated layout enhancement flow
The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Merging Formal and Simulation Verification Metrics for Coverage Closure
Minimize Power Consumption with A Novel Power ECO Flow
Mitigation of Soft-Errors in Storage Elements through Layout and Circuit Design Techniques
A Novel Duty-Cycle Adjuster Circuit , To Be Used As Part Of Automatic Clock Duty-Cycle Corrector Circuit
On-Chip embedded sensor in 18nm technology to monitor the effects of process variations on standard cells logic and interconnect delays
Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Path-Finding Through Variability-Aware DTCO-Flow
Performance Optimization of Embedded FPGA
Porting software to hardware using XLS/DSLX
Process Monitoring Blocks - for Monitoring Analog Performance
Science Without Boundaries: A Proven Method To Achieve Seamless Design Collaboration between Cross-Institutional Project Teams
Shift Left Performance Verification using Formal Methods for ML ASICs
Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
Technology co-optimization to mitigate the technology impact of context-based timing in standard Cell library
Physically Unclonable Function Compliant with ISO/IEC 20897-1:2020
Is Front-End Analog Design Automation an NP-type or simply a P-type problem ?