Special Session (Research): Breaking Down Physical Design Barriers with Open and Agile Flow Tools
Event TypeSpecial Session (Research)
TimeWednesday, July 13th1:30pm - 3:00pm PDT
Location3003, Level 3
DescriptionOpen-source EDA tools, open-source RTL & physical IP, and open-source PDKs are democratizing chip design, but the complete physical design process still requires 10-50 tool steps organized into complex flows specialized for every unique combination of tools, IP, and PDKs. This session includes three presentations on novel flow tools that are attempting to address this challenge from different perspectives including new flow tool generators with a strong emphasis on modularity and reusability and a new distributed-systems approach to enable warehouse-scale execution of sophisticated flows. The flow tools presented in this session represent the state-of-the-art in this area and have been used in over a dozen tapeouts on technologies ranging from 180nm down to 12nm. The goal for the session is to spark discussion around open and agile flow tools, while also encouraging future research in the EDA community on flow tool abstractions, programming languages, systems, and optimizations.