Special Session (Research): New Perspectives in High-Level Synthesis
Event TypeSpecial Session (Research)
TimeWednesday, July 13th3:30pm - 5:30pm PDT
Location3003, Level 3
DescriptionThe ever-increasing complexities in semiconductor manufacturing are driving a renewed interests in techniques and approaches to generate hardware implementation quickly and effectively starting from high-level algorithmic specifications. High-Level Synthesis (HLS) has been subject of research for several decades, leading to numerous tools able to convert specifications written in general purpose languages (typically C or C++, with progressively more coverage of the syntaxes) to implementations in hardware description languages, used for both field programmable gate arrays (FPGAs) and Application-Specific Integrated Circuit (ASIC). However, new requirements and challenges brought by new technology nodes are leading HLS to explore new applications and creating new opportunities. These include ability to synthesize starting from higher level, high productivity programming frameworks (for data science and machine learning), their integration in agile hardware design flows, complex parallel accelerator architectures, integration of novel methods (including artificial intelligence and surrogate models) and dimensions for design space exploration (real time and security guarantees), and even new applications (e.g., HLS to enable functional verification of complex ASICs). This special session investigates all these new perspectives for HLS with four talks for leading experts of the area.