Networking Reception, Work-in-Progress Poster: Networking Reception & Work-In-Progress Poster Session
Event TypeNetworking Reception, Work-in-Progress Poster
TimeWednesday, July 13th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
Aggressive Performance Improvement on PIM Devices by Adopting Hugepages
Agile: A Collaborative Air-ground IoT Edge Framework for Sustainable Remote Monitoring
Aging-aware Critical Path Selection via Graph Attentional Networks
Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Ambient Temperature Estimation using Neural Networks and Device Contextual Information
AMBITION: Ambient Temperature Aware VM Allocation for Energy Efficient Edge Data Centers
Attacking the TimingCamouflage+ Algorithm
Automatic Generation of Cell Based structured CIM Macros
Automation of Functional Safety and Security Methods for Design and Verification
AutoPilot: Compute Design Automation for Autonomous Drones
Bounded BaT: Bounded Backup Time for Intermittent Power Devices
A Built-In Adaptive NDA for High-Level Language Acceleration
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs
Constructing Large Buffers with HeterogeneousSTT-RAM Cells for DNN Accelerators
A Coq Framework for More Trustworthy DRAM Controllers
Deep Reinforcement Learning Empowered Content Caching in Mobile Social Networks
Design Space Exploration of Streaming Implementations of CNNs on the Xilinx AIEngine Processor Array
A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms
An Efficient Analog Convolutional Neural Network Hardware Accelerator Enabled by a Novel Memoryless Architecture for Insect-Sized Robots
Efficient Scheduling of Synchronous Dataflow Graphs on Communication Cost-Aware Heterogeneous Platforms
An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Equivalence Checking for Agile Hardware Design
Error Distribution Modeling for Behavior-level Approximate Computing
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator
Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information
Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Instant Data Sanitization on Multi-Level-Cell NAND Flash Memory
Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
LDAVPM: A Latch Design with Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments
Leveraging Layout-based Effects for Locking Analog ICs
A method for hierarchical, transistor-level circuit simulation
ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
A Model-Based Evaluation Framework for Battery Cell Balancing Techniques
Modular software for real-time quantum control systems
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
A Page-mapping Consistency Protecting Method for Soft Error Damage in Flash-based Storage
Performance Impact of Inter-PIM Communication
Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
PRIME: A PRocessing In Memory HardwareEmulation Framework
Qualification of Metamorphic Relations for System Level AMS Models using Data Flow Coverage
Real-time, personalized prediction of sepsis onset using fusion of electronic medical records and in-sensor analog classifier
A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
Self-Organizing and Parallel-Process Driven Fast Generation of Adversarial Examples for 3D Point Clouds
SoC Platform for Heterogeneous Multiple IP Core Evaluation
Soft Tiles: capturing physical implementation flexibility for tightly-coupled parallel processing clusters
System-Level Design and Target Agnostic High-Level Optimizations for HLS
Thermal and Signaling Considerations for 2.5D Integration of Arm-based 7nm High-Performance Systems
Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
Transformed Data and Faster-SPDZ : Techniques for Privacy-Preserving Deep Learning in Real-World Applications
A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Vector In Memory Architecture for simple and high efficiency computing
What Helper Data Really Leaks: A Practical Approach to Estimate the Min-Entropy in PUFs Using Their Response Mass Function
Fast In-Memory Floating-Point Addition
A Reinforcement Learning based Global Router