Networking Reception, Work-in-Progress Poster: Networking Reception & Work-In-Progress Poster Session
Event TypeNetworking Reception, Work-in-Progress Poster
TimeTuesday, July 12th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
Accelerating Data Analytics near Memory: A k-NN Search Case Study
Adaptive Sparsity-Aware Cloud Offloading for Edge DNN Inference
Addressing Ordering Woes of PCIe with Formal Verification
AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Bit-FLEX: an Energy-Efficient Analog-Digital Hybrid DNN Accelerator with Bit-Level Flexible Scalability
Bridger: Fast Token Delivery in Elastic Circuits
Building Efficient Portfolio-based Hardware Model Checker via And-Inverter Graph Structure Encoding
CharTM: An Efficient and Accurate Timing Yield Analysis Method for Memory Characterization based on Generalized Pareto Distribution
Circumventing Machine Learning-Based Attacks to Logic Locking
CoCo-FL: Communication- and Computation-Aware Federated Learning via Partial NN Freezing and Quantization
A Custom Macro Suite for Optimization of Neuromorphic TNN Designs in CMOS
Deep Learning Empowered Spectrum Sensing and Access in Distributed Cognitive Radio Network
Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Display Pixel Layout Design with Deep Reinforcement Learning
EA-Prune: Environment Adaptive Neural Network Pruning for Low-power Energy Harvesting Devices
Enabling Versatile Power Management for AIoT Devices
Endurance-Aware Deep Neural Network Real-Time Scheduling on ReRAM Accelerators
Energy Profiling of USB DNN Accelerators
ES4D: Accelerating Exact Similarity Search for High-Dimensional Vectors via Vector Slicing and In-SSD Distance Calculation
Exploring Input Data Obfuscation as a Countermeasure to Model Extraction Attacks on Deep Neural Networks
Fingerprinting Workloads for Reconfigurable Shared Accelerators
FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter
FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Graph Partitioning Approach for Fast Quantum Circuit Simulation
Heterogeneous Chiplet-based Architecture for In-Memory Acceleration of DNNs: A Big-Little Approach
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Joint Resource Scheduling in Wireless Networked Control Systems with Energy Constraint
Lego: Dynamic Multi-Chip-Module Resource Provision Architecture for Multi-Tenant DNNs
A Linear Column-Major Capacitance Multiplier based Analog In-Memory Computing Architecture
Logic Locking Based Trojans: A Friend Turns Foe
LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Novel ML based Reconfigurable Macro Placement for SoC Design
On the (in)security of Memory Protection Units
par-gem5: Parallelizing gem5’s Atomic Mode
Physics-Consistent Thermal SPICE and Multi-Correlated Recurrent Neural Networks to Simulate Sophisticated FinFET Circuitry
PowerSynth 2: A High-Density and Heterogeneous Power Electronics Physical Design Automation Framework
A Proposition for Computing System Design Automaticity and Correctness Potential
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-Core MCUs through Performance-Driven Autotuning
Quantum Multiple-Valued Decision Diagrams with Linear Transformations
RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Rubik’s Optical Neural Networks: Multi-task Learning with Physics-aware System and Algorithms
A Secure Design Methodology to Prevent Targeted Trojan Insertion During Fabrication
Tackling Resource Utilization in DNN Accelerators
TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Two-level Hierarchical Cluster-Node Scheduling for Heterogeneous Datacenters
Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
X-on-X Simulation: Distributed Parallel SystemC TLM Virtual Platforms for Heterogeneous Systems
You Already Have It: A Generator-Free Low-Precision DNN Training Framework using Stochastic Rounding
WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems
Neural Network Layer Assignment for Distributed Inference via Integer Programming
AI-Driven Accelerometer-Based Bird Activity Recognition