Session Full Program · Contributors · Organizations · Search Program · My Agenda · Happening NowMore…Search ProgramMy AgendaHappening NowNetworking Reception, Work-in-Progress Poster: Networking Reception & Work-In-Progress Poster SessionEvent TypeNetworking Reception, Work-in-Progress PosterTimeTuesday, July 12th6:00pm - 7:00pm PDTLocationLevel 2 LobbyPresentationsAccelerating Data Analytics near Memory: A k-NN Search Case StudyAuthorsMinho HaJoonseop SimJungmin ChoiDonguk MoonMyunghyun RheeTaeyoung AhnByungil KohEuicheol LimKyoung ParkAdaptive Sparsity-Aware Cloud Offloading for Edge DNN InferenceAuthorsMarina NeseemAbdelrahman HosnySherief RedaAddressing Ordering Woes of PCIe with Formal VerificationAuthorsVedprakash MishraCarlston LimZhi Feng LeeJian Zhong WangAnshul JainAchutha KiranKumar V MAI/ML Driven Self-adaptive Design Methodology for Analog CircuitsAuthorsKoushik DeDeepthi AmuruAbhishek PullelaAshfakh AliAndleeb ZahraBattu Yadavmounika kelamAshutosh PathyGaurav DixitKhanh LeZia AbbasBit-FLEX: an Energy-Efficient Analog-Digital Hybrid DNN Accelerator with Bit-Level Flexible ScalabilityAuthorsDonghyeon YiInjun ChoiGichan YunEdward ChoiSohmyung HaIk Joon ChangMinkyu JeBridger: Fast Token Delivery in Elastic CircuitsAuthorsAyatallah ElakhrasAndrea GuerrieriLana JosipovicPaolo IenneBuilding Efficient Portfolio-based Hardware Model Checker via And-Inverter Graph Structure EncodingAuthorsChengyu ZhangJiayi ZhuYihao HuangJianwen LiGeguang PuMoshe vardiCharTM: An Efficient and Accurate Timing Yield Analysis Method for Memory Characterization based on Generalized Pareto DistributionAuthorsLiang PangXiao Shilongxin Shihao yanCircumventing Machine Learning-Based Attacks to Logic LockingAuthorsYinghua HuSubhajit Dutta ChowdhuryKaixin YangMustafa MunirJatin BollareddyPierluigi NuzzoCoCo-FL: Communication- and Computation-Aware Federated Learning via Partial NN Freezing and QuantizationAuthorsKilian PfeifferMartin RappRamin KhaliliJoerg HenkelA Custom Macro Suite for Optimization of Neuromorphic TNN Designs in CMOSAuthorsHarideep NairPrabhu VellaisamySantha BhasuthkarJohn Paul ShenDeep Learning Empowered Spectrum Sensing and Access in Distributed Cognitive Radio NetworkAuthorsKeke GaiYue ZhangMeikang QiuLiehuang ZhuDesign Space Exploration of Mixed-Precision Hardware Accelerators for CNNsAuthorsCecilia LatotzkeTim CiesielskiTobias GemmekeDisplay Pixel Layout Design with Deep Reinforcement LearningAuthorsByeong Keun KangHyung Joon NamIn HuhJae Keon BaeJeong Hyeon ChoiKi Seok ChangWoohyung LimIl Ho KimSeok Woo LeeSoo Young YoonEA-Prune: Environment Adaptive Neural Network Pruning for Low-power Energy Harvesting DevicesAuthorsSahidul IslamShanglin ZhouYueying LiangRan RanYufang JinWujie WenCaiwen DingMimi XieEnabling Versatile Power Management for AIoT DevicesAuthorsXiaofeng HouXuehan TangJiacheng LiuChao LiLuhong LiangTim ChengEndurance-Aware Deep Neural Network Real-Time Scheduling on ReRAM AcceleratorsAuthorsSHI SHAAjinkya BankarXiaokun YangWujie WenGang QuanEnergy Profiling of USB DNN AcceleratorsAuthorsMatthias WessMatvey IvanovNikolas AlgeChristian KriegAxel JantschES4D: Accelerating Exact Similarity Search for High-Dimensional Vectors via Vector Slicing and In-SSD Distance CalculationAuthorsJuhwan KimJong Sun SeoJong-Hyeok ParkSang-Won LeeHongchan RohHyungmin ChoExploring Input Data Obfuscation as a Countermeasure to Model Extraction Attacks on Deep Neural NetworksAuthorsBrooks OlneyRobert KaramFingerprinting Workloads for Reconfigurable Shared AcceleratorsAuthorsParnian MokriMark HempsteadFLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal SemiperimeterAuthorsSven ThijssenSumit JhaRickard EwetzFSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator ArchitectureAuthorsYingnan ZhaoKe WangAhmed LouriAvinash KaranthRazvan BunescuGraph Partitioning Approach for Fast Quantum Circuit SimulationAuthorsJaekyung ImSunghye ParkSeokhyeong KangHeterogeneous Chiplet-based Architecture for In-Memory Acceleration of DNNs: A Big-Little ApproachAuthorsGokul KrishnanSumit MandalChaitali ChakrabartiJae-sun SeoUmit OgrasYu CaoHPVM2FPGA: Enabling True Hardware-Agnostic FPGA ProgrammingAuthorsAdel EjjehLeon MedvinskyAaron CouncilmanHemang NehraSuraj SharmaVikram AdveLuigi NardiEriko NurvitadhiRob RutenbarImplementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGAAuthorsKevin NamHyunyoung OhSanghyuk HeoHyungon MoonYunheung PaekJoint Resource Scheduling in Wireless Networked Control Systems with Energy ConstraintAuthorsVincent ChauChenchen FuShu HanSong HanMinming LiPeng WuYingchao ZhaoLego: Dynamic Multi-Chip-Module Resource Provision Architecture for Multi-Tenant DNNsAuthorsChing-Jui LeeYu Xuan ZhouTsung Tai YehA Linear Column-Major Capacitance Multiplier based Analog In-Memory Computing ArchitectureAuthorsKailash PrasadAditya BiswasArpita KabraJoycee MekieLogic Locking Based Trojans: A Friend Turns FoeAuthorsYuntao LiuAruna JayasenaPrabhat MishraAnkur SrivastavaLogicWiSARD: Memoryless Synthesis of Weightless Neural NetworksAuthorsIgor MirandaZachary SusskindAman AroraLuis VillonRafael KatopodisLeandro AraújoDiego DutraPriscila LimaFelipe FrançaLizy JohnMauricio BreternitzMentha: Enabling Sparse-Aware Computation on Systolic ArraysAuthorsMinjin TangMei MenYasong CaoJunzhong ShenJianchao YangJiawei FeiYang GuoSheng LiuMulti-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive LogicAuthorsXi LiMin PanTong LiuPeter BeerelMuZero-guided Simulated Annealing for Nanometer Circuit PlacementAuthorsWei-Hao ChangKai-En YangGao-Yi ChaoYu-Hsun ChenChen-Feng ChiangYen-Min TsaiSau-Loong LowChia-Shun YehBun-Suan HengChia-Yu TsaiChin-Tang LaiHung-Hao ShenNovel ML based Reconfigurable Macro Placement for SoC DesignAuthorsudarshanam kommanaboyinaOn the (in)security of Memory Protection UnitsAuthorsMichele GrisafiMahmoud AmmarBruno Crispopar-gem5: Parallelizing gem5’s Atomic ModeAuthorsNiko ZurstraßenJosé Cubero-CascanteJan JosephLi YichaoXie XinghuaRainer LeupersPhysics-Consistent Thermal SPICE and Multi-Correlated Recurrent Neural Networks to Simulate Sophisticated FinFET CircuitryAuthorsChia-Che ChungTao ChouBo-Wei HuangHsin-Cheng LinChia-Jung TsenC. W. LiuPowerSynth 2: A High-Density and Heterogeneous Power Electronics Physical Design Automation FrameworkAuthorsImam Al RaziQuang LeH. Alan MantoothYarui PengA Proposition for Computing System Design Automaticity and Correctness PotentialAuthorTage MohammadatPULP-TrainLib: Enabling On-Device Training for RISC-V Multi-Core MCUs through Performance-Driven AutotuningAuthorsDavide NadaliniManuele RusciGiuseppe TagliaviniLeonardo RavagliaLuca BeniniFrancesco ContiQuantum Multiple-Valued Decision Diagrams with Linear TransformationsAuthorsYonghong LiHao MiaoHaipeng CheLiangda FangQuanlong GuanHuanming ZhangRankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on EdgeAuthorsChanghai ManCheng ChangChenchen DingAo ShenHongwei RenZiyi GuanYuan ChengShaobo LuoHao YuRFR: An STT-MRAM Cache Management Scheme for Retention Failure ReductionAuthorsAbdollah MohammadiElham CheshmikhaniHossein AsadiRubik’s Optical Neural Networks: Multi-task Learning with Physics-aware System and AlgorithmsAuthorsYingjie LiWeilu GaoCunxi YuA Secure Design Methodology to Prevent Targeted Trojan Insertion During FabricationAuthorsArjun SureshSiva Nishok DhanuskodiDaniel HolcombTackling Resource Utilization in DNN AcceleratorsAuthorsIris UwizeyimanaNatalie Enright JergerTrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.AuthorsMuhammed Kawser AhmedSujan Kumar SahaJoel Mandebi MbongueChristophe BobdaTwo-level Hierarchical Cluster-Node Scheduling for Heterogeneous DatacentersAuthorsWenkai GuanCristinel AbabeiUnraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILPAuthorsDake ChenXuan ZhouPeter BeerelX-on-X Simulation: Distributed Parallel SystemC TLM Virtual Platforms for Heterogeneous SystemsAuthorsLukas JüngerSimon WintherRainer LeupersYou Already Have It: A Generator-Free Low-Precision DNN Training Framework using Stochastic RoundingAuthorsGeng YuanSung-En ChangQing JinAlec LuYanyu LiYushu WuZhenglun KongYanyue XiePeiyan DongXiaolong MaXulong TangMinghai QinZhenman FangYanzhi WangWESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing SystemsAuthorsJiangwei ZhangChong WangYi CaiZhenhua ZhuDonald Kline, JrGuohao DaiHuazhong YangYu WangNeural Network Layer Assignment for Distributed Inference via Integer ProgrammingAuthorsRobert ViramontesAzadeh DavoodiAI-Driven Accelerometer-Based Bird Activity RecognitionAuthorsOliver HarmsJanek HabererSukanya MorbaleOlaf Lansiedel