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DTSTAMP:20220715T000418Z
LOCATION:3007\, Level 3
DTSTART;TZID=America/Los_Angeles:20220713T103000
DTEND;TZID=America/Los_Angeles:20220713T105200
UID:dac_DAC 2022_sess118_RESEARCH604@linklings.com
SUMMARY:Floorplanning with Graph Attention
DESCRIPTION:Research Manuscript\n\nFloorplanning with Graph Attention\n\nL
 iu, Ju, Li, Dong, Zhou...\n\nFloorplanning has long been a critical physic
 al design task with high computation complexity. Its key objective is to d
 etermine the initial locations of macros and standard cells with optimized
  placement wirelength. This paper presents a graph attention-based floorpl
 anning method to learn an optimized mapping between netlist interconnectio
 n and physical wirelength, and then generate a chip floorplan with high co
 mputation efficiency, which then drives the downstream mixed-size physical
  placement task. Experimental studies using both benchmarks and industrial
  designs demonstrate that compared to state-of-the-art mixed-size placers,
  the proposed method improves placement runtime by 15\% on average with re
 duces physical wirelength.\n\nTopic: EDA\n\nKeyword: Physical Design and V
 erification, Lithography and DFM
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