BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20220715T000417Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20220712T105200
DTEND;TZID=America/Los_Angeles:20220712T111500
UID:dac_DAC 2022_sess138_RESEARCH421@linklings.com
SUMMARY:PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
DESCRIPTION:Research Manuscript\n\nPHANES: ReRAM-based Photonic Accelerato
 rs for Deep Neural Networks\n\nLIU, Liu, Fu, Chen, Zhang...\n\nResistive-r
 andom-access-memory has demonstrated promises of in-situ matrix-vector-mul
 tiplications to accelerate deep neural networks. However, subject to intri
 nsic properties of analog processing, most proposed ReRAM-based accelerato
 rs require excessive costly ADC/DAC to avoid distortion of electronic-anal
 og signals during inter-tile transmission. This paper presents a novel pho
 tonic-accelerator architecture (PHANES), which utilizes optical interconne
 cts to achieve high-fidelity analog-analog links. Such paradigm calculates
  partial-sum during the optical transmission to reduce ADC/DAC and shift-a
 dders. To circumvent memory-wall problem, we further propose a progressive
  bit-depth technique. Evaluations show that PHANES improves system energy-
 efficiency-per-area (TOPS/W/mm2) by 26.2x compared to state-of-the-art des
 igns, with great potentials of scalability towards very-large-scale accele
 rators.\n\nTopic: Design\n\nKeyword: In-memory and Near-memory Computing
END:VEVENT
END:VCALENDAR