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BEGIN:VEVENT
DTSTAMP:20220715T000416Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20220711T113000
DTEND;TZID=America/Los_Angeles:20220711T114500
UID:dac_DAC 2022_sess159_FEDES112@linklings.com
SUMMARY:Formal verification contract based micro architectural analysis of
  Server SoC's
DESCRIPTION:Engineering Tracks, Front-End Design\n\nFormal verification co
 ntract based micro architectural analysis of Server SoC's\n\nMumbaikar, so
 od, Munigala, n\n\nThe most challenging task in System on Chip (SoC) desig
 n is in it’s validation and an assurance that validation covers enti
 re design exhaustively, is ensured using various assertion property and co
 verage metrics. Server System on Chip (SoC) are power and performance gree
 dy designs. Consequently, micro analysis such SoC Holds prominence. Such a
 nalysis with existing validation infrastructure cannot be achieved because
  of the enabling all assertions at SoC leads to increase in simulation tim
 e and logs have huge data and difficult to analysis. Also, assertion enabl
 ed test takes huge amount of time for simulation. Moreover, selective asse
 rtions enablement is not seamless in validation infrastructure. Functional
  coverage analysis of such features must be timing accurate from IP to SOC
 , such type of coverage analysis is not done in standard coverage paradigm
  on SoC. We address this problem by developing an offline Temporal logic-b
 ased query mechanism. This mechanism provides us to write simple Linear Te
 mporal Logic (LTL) properties (called as queries in this case) to Timed Li
 near Temporal Logic (TTL) and helps realize an offline formal verification
  engine. The framework helps debug the waveform database as TTL queries an
 d results are returned within few minutes, consequently, making micro arch
 itecture analysis easy. Moreover, this solution comes with a package of ma
 ny allied benefits. We claim to improve the micro architecture analysis ef
 fort as we get a speedup of the order of 4x while debugging failed scenari
 os, as well as significant improvement in coverage analysis.\n\nTopic: Fro
 nt-End Design
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