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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20220715T000416Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20220711T110000
DTEND;TZID=America/Los_Angeles:20220711T111500
UID:dac_DAC 2022_sess170_ESS106@linklings.com
SUMMARY:Rapid Embedded Software Verification Through Hardware-Accelerated,
  Parallel SystemC TLM Simulation - A RISC-V Example
DESCRIPTION:Embedded Systems and Software, Engineering Tracks\n\nRapid Emb
 edded Software Verification Through Hardware-Accelerated, Parallel SystemC
  TLM Simulation - A RISC-V Example\n\nJünger, Leupers\n\nToday’s complex H
 W/SW systems require functional target software verification as early as p
 ossible in the design cycle to meet tight release schedules. Full-system-s
 imulators, so called Virtual Platforms (VPs), built on the SystemC TLM-2.0
  standard are the go-to tool for this job. However, due to increasing targ
 et system complexity, construction of high-performance VPs for interactive
  use is posing a growing challenge.\n\nIn this work we demonstrate how VP 
 performance can be increased using our parallel, hardware-accelerated Syst
 emC TLM-2.0 simulation technology. We present speedups of 3.6x for compute
  intensive workloads in our RISC-V case study. In addition, we exhibit the
  capabilities of our technology in a representative, interactive demonstra
 tion.\n\nTopic: Embedded Systems, RISC-V
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