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BEGIN:VEVENT
DTSTAMP:20220715T000511Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20220711T170000
DTEND;TZID=America/Los_Angeles:20220711T180000
UID:dac_DAC 2022_sess186_ETPOST102@linklings.com
SUMMARY:A Dynamic approach towards NOC Performance Verification in Pre-Sil
 icon and Overcome the traditional Overheads
DESCRIPTION:Engineering Track Poster, Engineering Tracks\n\nA Dynamic appr
 oach towards NOC Performance Verification in Pre-Silicon and Overcome the 
 traditional Overheads\n\nVasu, Mohammad, Chakravarthy\n\nPerformance is th
 e most important source of competitive advantage for modern SOCs and NOC i
 s the one of the most important backbones of the SOCs which helps to accom
 plish that. The performance verification of the NOC is the very significan
 t on top of the functionality. Since there are diverse ways of configuring
  the SOCs – different IP and interconnect topologies, number of masters an
 d slaves, bus widths, packet sizes, clock speeds, enabling performance ver
 ification early during the design cycle and scaling it up to different lev
 els for environment gets overwhelming. To achieve the multiple level of pe
 rformance verification in an SOC, there is a persistent need for novel app
 roach for performance analysis and debug during earlier design cycle.\nThe
  proposed solution is using the AMBA VIPs and third-party Performance Anal
 yzer for automated protocol performance analysis and debug. This verificat
 ion methodology has provided enormous gain in multiple levels of NOC perfo
 rmance verification in an SOC and from the first test case itself we are a
 ble to start on the performance analysis. This approach has enabled us to 
 provide meaning performance analysis data to the design and architecture t
 eam, fixed the design issues, NOC generation tool issues and able to achie
 ve the expected performance in the silicon.\n\nTopic: AI, Back-End Design,
  Cloud, Embedded Systems, Front-End Design, IP
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