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LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2022_sess187_ETPOST193@linklings.com
SUMMARY:Minimum repeater addition ECOs for power efficient designs
DESCRIPTION:Engineering Track Poster, Engineering Tracks\n\nMinimum repeat
 er addition ECOs for power efficient designs\n\nPandya, Rao\n\nMinimum rep
 eater addition ECOs for power efficient designs \n\nWith the shrinking dev
 ices and popularity of portable high speed electronic gadgets power consum
 ption and dissipation has become an important as well as challenging topic
  in VLSI circuit design. Low power circuit design can be capitalized at va
 rious levels in IC design cycle. During backend implementation, even after
  systematic implementation of the design using various power optimization 
 techniques, power-aware timing ECO’s become very important to contain desi
 gn power.\n\nAfter synthesis and automatic place & route (APR) cycle, timi
 ng and design rule violations (maximum allowed transition time and capacit
 ive load in data and clock path) remain which are not fixed by tool due to
  design constraints, optimization priority, construction to signoff miscor
 relation etc. An easy method to fix the remaining timing violations is to 
 insert repeater (buffers and inverters) in clock or data path as long as i
 t is not degrading other timing metrics. However, repeater addition adds t
 o design power. In this paper we will discuss ECO techniques that designer
 s can use to close timing and design rule violations with minimum repeater
  addition and show how systematic use of these techniques through automati
 on can help save design power.\n\nTopic: AI, Back-End Design, Cloud, Embed
 ded Systems, Front-End Design, IP
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