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DTSTAMP:20220715T000421Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20220714T160000
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UID:dac_DAC 2022_sess217_SPSSN112@linklings.com
SUMMARY:High-level design methods for hardware security: Is it the right c
 hoice?
DESCRIPTION:Special Session (Research)\n\nHigh-level design methods for ha
 rdware security: Is it the right choice?\n\nPilato, Sciuto, Garg, Karri\n\
 nDue to the globalization of the electronics supply chain, hardware engine
 ers are increasingly interested in modifying their chip designs to protect
  their intellectual property (IP) or the privacy of the final users. Howev
 er, the integration of the state-of-the-art solutions for hardware and har
 dware-assisted security is not fully automated, requiring the amendment of
  stable tools and industrial tool chains. This significantly limits the ap
 plication in industrial designs, potentially affecting the security of the
  resulting chips. \nWe discuss how existing solutions can be adapted to im
 plement security features at higher levels of abstractions (during high-le
 vel synthesis or directly at the register-transfer level) and complement c
 urrent industrial design and verification flows. Our modular framework all
 ows designers to compose these solutions and create additional protection 
 layers.\n\nTopic: Security
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