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DTSTART:19700308T020000
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DTSTAMP:20220715T000418Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20220713T160000
DTEND;TZID=America/Los_Angeles:20220713T163000
UID:dac_DAC 2022_sess218_SPSSN107@linklings.com
SUMMARY:Accelerator Design with Decoupled Hardware Customizations: Benefit
 s and Challenges
DESCRIPTION:Special Session (Research)\n\nAccelerator Design with Decouple
 d Hardware Customizations: Benefits and Challenges\n\nPal, Lai, Xiang, Yan
 g, Cocchini...\n\nCurrent High-Level Synthesis (HLS) programming models en
 tangle algorithm specifications with hardware customization techniques, wh
 ich lowers both the productivity and portability of the accelerator design
 . To solve this problem, recent work such as HeteroCL proposes to decouple
  algorithm definition from essential hardware customization techniques in 
 compute, data type, and memory. While the decoupling of the algorithm and 
 customizations provides benefits to the compilation/synthesis process, the
 y also create new hurdles for the programmers to debug and validate the co
 rrectness of the optimized design. In this work, using realistic ML applic
 ations, we first explain the advantages of the decoupled programming model
 . Using the same case studies, we further show how seemingly benign usage 
 of the customization primitives can lead to new challenges to verification
 . We then outline the research opportunities and discuss some of our recen
 t efforts as the first step to enable a robust and viable verification sol
 ution in the future.\n\nTopic: EDA
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