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Presentation

Minimum repeater addition ECOs for power efficient designs
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionMinimum repeater addition ECOs for power efficient designs

With the shrinking devices and popularity of portable high speed electronic gadgets power consumption and dissipation has become an important as well as challenging topic in VLSI circuit design. Low power circuit design can be capitalized at various levels in IC design cycle. During backend implementation, even after systematic implementation of the design using various power optimization techniques, power-aware timing ECO’s become very important to contain design power.

After synthesis and automatic place & route (APR) cycle, timing and design rule violations (maximum allowed transition time and capacitive load in data and clock path) remain which are not fixed by tool due to design constraints, optimization priority, construction to signoff miscorrelation etc. An easy method to fix the remaining timing violations is to insert repeater (buffers and inverters) in clock or data path as long as it is not degrading other timing metrics. However, repeater addition adds to design power. In this paper we will discuss ECO techniques that designers can use to close timing and design rule violations with minimum repeater addition and show how systematic use of these techniques through automation can help save design power.