Floorplanning with Graph Attention
TimeWednesday, July 13th10:30am - 10:52am PDT
Location3007, Level 3
Physical Design and Verification, Lithography and DFM
DescriptionFloorplanning has long been a critical physical design task with high computation complexity. Its key objective is to determine the initial locations of macros and standard cells with optimized placement wirelength. This paper presents a graph attention-based floorplanning method to learn an optimized mapping between netlist interconnection and physical wirelength, and then generate a chip floorplan with high computation efficiency, which then drives the downstream mixed-size physical placement task. Experimental studies using both benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers, the proposed method improves placement runtime by 15\% on average with reduces physical wirelength.