High-level design methods for hardware security: Is it the right choice?
TimeThursday, July 14th4pm - 4:30pm PDT
Location3003, Level 3
Special Session (Research)
DescriptionDue to the globalization of the electronics supply chain, hardware engineers are increasingly interested in modifying their chip designs to protect their intellectual property (IP) or the privacy of the final users. However, the integration of the state-of-the-art solutions for hardware and hardware-assisted security is not fully automated, requiring the amendment of stable tools and industrial tool chains. This significantly limits the application in industrial designs, potentially affecting the security of the resulting chips.
We discuss how existing solutions can be adapted to implement security features at higher levels of abstractions (during high-level synthesis or directly at the register-transfer level) and complement current industrial design and verification flows. Our modular framework allows designers to compose these solutions and create additional protection layers.